2022.10.06
Chiplet integration technology with simplest scheme
Scalability of inter-chip bandwidth and integration scale
A research team consisting of Specially Appointed Professor Yoichiro Kurita (Laboratory for Future Interdisciplinary Research of Science and Technology, Institute of Innovative Research, Tokyo Institute of Technology (Tokyo Tech) and a collaborative research company have developed chiplet integration technology that uses a technology called “Pillar-Suspended Bridge (PSB).” This technology meets the requirements for broadband chip-to-chip communication and scalable chiplet integration, which is required for future large-scale chiplet integration, with a minimal configuration and manufacturing process.
It features a silicon bridge interconnection structure via a fine “MicroPillar” for broadband communication between chips and a manufacturing process called “All Chip-last.” The structure and the process provide the requirements for chiplet integration in the simplest form. This technology is expected to accelerate the evolution of future semiconductor integrated circuit system technology, replacing miniaturization, which is predicted to slow down.
This research was conducted jointly with Aoi Electronics Co., Ltd. and four other companies ahead of the Chiplet Integration Platform Consortium (described later) to be established on October 1. Detailed results will be presented at the international conference IMAPS 2022, which will be held in Boston, USA, starting October 3 (Monday) at 10 p.m. (Japan time).
In addition to Tokyo Tech, the Chiplet Integration Platform Consortium is centered on Osaka University (Specially Appointed Professor and Professor Emeritus Katsuaki Suganuma) and Tohoku University (Associate Professor Takafumi Fukushima), and 32 companies are scheduled to participate (as of September 2022). It covers research on chiplet integration platform technology in general, including 3D integration technology and optical integration technology.
